morgenall-logo

ASIC RTL DESIGN ENGINEER / 6 - 10 Years / Bangalore

Bangalore

Posted 24 May 2017 (148 days ago)


Job Description

RTL Engineer in -ASIC Flows LINT CDC (Clark Domain Crossing) DRC rule checking & Synthesis using RTL compiler Develop micro-architecture and RTL implementation Block level/ full chip integration and design. Experience on ASIC At least 3+ years experience with design, verification and timing tools such as those from Synopsys/Cadence Hands-on with Lint, CDC, LEC and preferably Low Power check tools Some experience of AXI/AHB Design in System Verilog and timing, performance & power optimizations Good understanding of design implementation flows and tools (Synthesis, STA, and DFT) Good knowledge of configuration tools and workflow tools: Clearcase/ClearQuest, etc.

Key Skills

ASIC, RTL, SOC Integration


Industry

Semiconductors

Employment Type

Full Time

Job Function

Engineering


Experience Required

6 - 10 Years


No Of Positions


Salary Offered

INR 1000000 - 2500000


Interview Locations

Client Location - Bangalore(Interview Mode - Face 2 Face)


Also Matched Jobs


Project Manager / Lead- SOC verification

Bangalore,India

Posted 22 Sep 2017(27 days ago)


Verification Engineer

Hyderabad,India

Posted 25 Jul 2017(86 days ago)


Post Silicon Validation Engineer

Bangalore,India

Posted 20 Jul 2017(91 days ago)


DFT Verification Engineer

Bangalore,India

Posted 03 Jul 2017(108 days ago)


DFT Engineer

Hyderabad,Bangalore,India

Posted 30 Jun 2017(111 days ago)