ASIC RTL DESIGN ENGINEER / 6 - 10 Years / Bangalore


Posted 24 May 2017 (206 days ago)

Job Description

RTL Engineer in -ASIC Flows LINT CDC (Clark Domain Crossing) DRC rule checking & Synthesis using RTL compiler Develop micro-architecture and RTL implementation Block level/ full chip integration and design. Experience on ASIC At least 3+ years experience with design, verification and timing tools such as those from Synopsys/Cadence Hands-on with Lint, CDC, LEC and preferably Low Power check tools Some experience of AXI/AHB Design in System Verilog and timing, performance & power optimizations Good understanding of design implementation flows and tools (Synthesis, STA, and DFT) Good knowledge of configuration tools and workflow tools: Clearcase/ClearQuest, etc.

Key Skills

ASIC, RTL, SOC Integration



Employment Type

Full Time

Job Function


Experience Required

6 - 10 Years

No Of Positions

Salary Offered

INR 1000000 - 2500000

Interview Locations

Client Location - Bangalore(Interview Mode - Face 2 Face)

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