DFT engineer - ATPG /DFT verification / 3 - 5 Years / Hyderabad


Posted 14 Jul 2017 (582 days ago)

Job Description

Solid understanding of DFT techniques is required
Experience in spyglass, scan compression, scan insertion and ATPG process 
Experience in MBIST 
Experience in analyzing and debugging simulation failures is required
Solid understanding of digital logic fundamentals is required
Strong knowledge of Mentor/Synopsys tool suite, simulators expertise in VCS/NCSIM is expected.
Experience in STA constraint development in DFT modes is a plus
Experience in LBIST and IJTAG is a plus
Experience in silicon bring-up and yield improvement is a plus

Desired Candidate

 Pattern Simulation with and without timing annotation and debugging simulation mismatches (Cadence Incisive).
Familiarity with WGL/TDL file formats.
Good skills in Scan compression techniques and Logic BIST.
Exposure to Memory BIST insertion tools (Preferably Logic Vision MBIST).
Good experience in Boundary Scan, JTAG concepts, Core testing using P1500.
Should have basic understanding of Tester requirements.
Should be good at doing synthesis and timing (RC and PT/Tempus).
Knowledge of formal verification using LEC.
Exposure to SoC level DFT will be a plus.
Experience on low power DFT is an added advantage.
Good communication Skills
Positive attitude 
Can manage time well and is passionate about his work.
Proactive well rounded individual 

Key Skills




Employment Type

Full Time

Job Function

Information Technology

Experience Required

3 - 5 Years

No Of Positions

Salary Offered

INR 1200000 - 1800000

Interview Locations

Client Location - Not Mentioned(Interview Mode - Face 2 Face)

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