DFT Engineer / 5 - 7 Years / Bangalore


Posted 26 Apr 2017 (638 days ago)

Job Description

Candidate will be responsible for DFT architecture and test methodology definition, and driving implementation, primarily for Scan-based (ATPG) testing of high-end SoCs.
DFT Engineer will interface with internal tool development teams and will be responsible for driving synergies that facilitate test insertion, clock design, and vector development automation.
Defining and executing DFT-related tool flows, spanning insertion, ATPG, as well as DFT requirements in front-to-back SoC implementation flows and need to test vector planning for bring-up and production, and hand-on ATE bring-up experience. DFT insertion and pattern generation, RTL, Gate, and timing back-annotated simulation.
DFT Engineer must front-end chip implementation including BIST or Scan insertion, synthesis, netlist generation, timing and logical equivalency checks, floor planning, budgeting, clock methodology and timing constraint management.
DFT Engineer must have experience in all aspects of chip development: from design specification, defining architecture, micro-architecture, RTL design and functional verification, Synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.
They must create DFT implementation plan, delegate to team members and tracking and must need to test mode timing support or debug and closure at full chip level.
Should have experience in analysing and debugging simulation failures is required.
Must have solid understanding of digital logic fundamentals is required.

Desired Candidate

DFT Engineer must have excellent track of pattern simulation and coverage analysis (preferred simulator expert Experience in ATPG, Scan, BIST and Mentor Test Kompress. 
Fundamentals of SCAN stuck-at and at-speed techniques and must be expertise in handling Mentor Graphics EDT logic. 
DFT Engineer should have knowledge on on chip clock controller (OCC).
Experience with Perl and TCL languages is required.
Must generate high quality manufacturing test patterns for stuck-at, transition fault models and through the use of on-chip test compression techniques.
Well versed with ATPG, Scan insertion, MBIST and Simulation knowledge. Hands on experience in solving DFT problems, simulation failures, ATPG coverage. 
Must experience in STA constraint development in DFT modes is a plus. 

Key Skills




Employment Type

Full Time

Job Function


Experience Required

5 - 7 Years

No Of Positions

Salary Offered

INR 2500000 - 2700000

Interview Locations

Not Mentioned

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