The candidate will be involved in design and verification of these cutting edge next generation solutions. The candidate will own a sub-system or module in all aspects of verification and responsible for DV signoff and closure. Specifically, the candidate will be responsible for verification of networking products for the protocols like iWarp/RDMA, TCP/IP, iSCSI, L2/L3 Switching, routing, Access etc

The candidate will be involved in design and verification of these cutting edge next generation solutions. The candidate will own a sub-system or module in all aspects of verification and responsible for DV signoff and closure. A strong background in ASIC verification with a minimum verification experience of around 4-8 years.  Must have following skills:

a)      Experienced in using advanced verification methodology and concepts. Having extensive experience in developing advanced verification environments using VMM/OVM/UVM/SystemVerilog/Vera on both module level or chip level with the use of constrained random verification techniques

b)      Strong in scripting languages perl, csh, awk, sed etc.

c)      Must have an experience in networking product architectures at least one of the protocols like iSCSI/iWarp/RDMA, L2/L3 Switching, routing, TCP/IP etc.

d)      MUST have experience in verifying embedded processors like TenSilica/ARM/MIPS/ etc., Must have setup the unit level and system level simulation environment for that.

e)      Desirable to have co-simulation experience (with processor and ASIC)

f)       Desirable to have candidate with architecture verification experience.

g)      Desirable of have proficiency in assembly and oops based programming languages.

The successful candidate should have experience in going through several ASIC Design/Verification cycles from architecting and creating of ASIC test environment (communications/networking related preferred) to full completion of the verification work

Education: BE/MS with Electrical/Computer Engineering or Computer Science with Embedded Processor integration experience.