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DV Engineer/HW (MC, HMA, MA) / 4 - 10 Years / Bangalore

Bangalore

Posted 24 Feb 2018 (143 days ago)


Job Description

Design Verification group of Chelsio communications, market and technology leader enabling the convergence of networking, storage and clustering traffic over high speed Ethernet, is looking for highly skilled verification engineers to verify the ASIC.

 

-              They will be responsible to develop test environment and tests  for Memory sub-system cluster consisting of Memory controller for eDRAM, SRAM, DDR4,

-             Knowledge of functioning of Advanced Memory Arbiter and Host Arbiter schema

-              Develop detailed test plans and execute the testplan,

-              Develop block and system-level test benches and verification environments; achieve complete coverage to ensure first working silicon.

-              Adding functional coverage for the environment.

-              Develop the required scripts and maintain throughout the project.

 

Requirement:

-              Strong programming experience using system Verilog

-              Must have worked on Verification of eDRAM, SRAM, DDR4 memory controller blocks, Good understanding of Advanced Memory Arbiters and arbitration verification

-              Must have thorough understanding of JDEC Memory standards, Memory controller functionality, Memory controller to PHY interface  etc

-               Must have hands on experience building complex verification environment

-               Must have worked with some of the industry standard VIPs as Memory models  , Denali Memory models


Company Description

It is a privately-held company headquartered in Sunnyvale, California with a design center located in Bangalore, India. It is a market and technology leader enabling the convergence of networking, storage and clustering traffic over high speed Ethernet. With the proliferation of massive data centers, equipment density and power consumption are more critical than ever. At the same time cloud computing and server virtualization are driving the need for more uniform designs than the traditional data-center architectures can offer. With its proven Terminator ASIC technology designed in more than 200 OEM platforms and the successful deployment of more than 400,000 ports, it has enabled unified wire solutions for LAN, SAN and cluster traffic. With its unique ability to fully offload TCP, iSCSI and iWARP protocols on a single chip, adapter cards unburden communications responsibilities and processing overhead from servers and storage systems, resulting in a dramatic

Key Skills

Advanced Memory Arbiter and Host Arbiter schema


Industry

Information Technology And Services

Employment Type

Full Time

Job Function

Not Mentioned


Experience Required

4 - 10 Years


No Of Positions


Salary Offered

INR 1500000 - 2500000


Interview Locations

Client Location - Not Mentioned(Interview Mode - Face 2 Face)


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