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Physical Design Engineer / 3 - 10 Years / Bangalore

Bangalore

Posted 05 May 2017 (166 days ago)


Job Description

Experience in Physical Design Execution is required Independent planning and execution of Netlist-to-GDSII. Ability to collaborate and resolve issues w.r.t. constraints validation, verification, STA, Physical design, etc. Work on methodology with help of local and external CAD/EDA teams for faster design convergence Should have good knowledge & experience in low power design implementation, high performance design closure & multi scenario timing convergence Well aware of place and route methodologies and hands on experience with timing convergence Well versed with the level timing closure (STA), timing closure methodologies, ECO generation and predictable convergence. Well versed with parasitic extraction, LVS/DRC and other Physical verification checks. Tcl scripting knowledge is mandatory. Shell / sed / awk / perl scripting knowledge preferred. Experience/Knowledge in Chip level Timing closure & Physical Design activities is preferred Should possess good debug skills. Expected to be a self-motivated & team worker. An excellent verbal and written communication is desired.

Key Skills

Physical Design, STA, CAD/EDA


Industry

Semiconductors

Employment Type

Full Time

Job Function

Information Technology


Experience Required

3 - 10 Years


No Of Positions


Salary Offered

INR 800000 - 2000000


Interview Locations

Client Location - Not Mentioned(Interview Mode - Face 2 Face)


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